The present invention is related to semiconductor devices and manufacturing and more particularly to high performance field effect transistors (FETS) and methods of manufacturing high performance FETS.
Typical semiconductor integrated circuit (IC) design goals include high performance and density at minimum power. To minimize semiconductor circuit power consumption, most ICs are made in the well-known complementary insulated gate field effect transistor (FET) technology known as CMOS. A typical CMOS circuit drives a purely or nearly pure capacitive load and includes paired complementary devices, i.e., an n-type FET (NFET) paired with a corresponding p-type FET (PFET), usually gated by the same signal. Performance depends upon how fast the CMOS circuit can charge and discharge the capacitive load, i.e., the circuit's switching speed. Since the pair of devices have operating characteristics that are, essentially, opposite each other, when one device (e.g., the NFET) is on and conducting (modeled simply as a closed switch), the other device (the PFET) is off, not conducting (ideally modeled as a simple open switch) and, vice versa. Thus, ideally, there is no static or DC current path in a typical CMOS circuit and the circuit load switches as fast as one switch can be closed and the other opened.
A CMOS inverter, for example, is a PFET and NFET pair that are series connected between a power supply voltage (Vdd) and ground (GND). Both are gated by the same input and both drive the same a capacitive load. At one input signal state the PFET is on pulling the output high, PFET on current charging the load capacitance to Vdd. At the opposite input signal state the NFET is on pulling the output low, NFET on current discharging the load capacitance back to ground. Device on current is related to gate, source and drain voltages and, depending upon those voltages, the device may be modeled as a voltage controlled current source or a resistor. Since series resistance, i.e., in the device drain or source, drops some voltage as current flows through the device, series resistances affect device voltages and so, affect (reduce) device current, slowing the charge or discharge of the capacitive load. The switch is open, i.e., the device is off, when the magnitude of the gate to source voltage (Vgs) is less than some threshold voltage (VT) with respect to its source. So, ideally, an NFET is off below VT, and on, conducting current above VT. Similarly, a PFET is off when its gate is above its VT,i.e., less negative, and on below VT.
Semiconductor technology and chip manufacturing advances towards higher circuit switching frequency (circuit performance) and an increased number of transistors (circuit density) for more function from the same area have resulted in a steadily decreasing chip feature size and, correspondingly, supply voltage. Generally, all other factors being constant, the active power consumed by a given unit increases linearly with switching frequency. Thus, not withstanding the decrease of chip supply voltage, chip power consumption has increased as well. Both at the chip and system levels, cooling and packaging costs have escalated as a natural result of this increase in chip power.
Unfortunately, as FET features have shrunk, device leakages including gate leakages (i.e., gate to channel, gate to source or drain and gate induced drain leakage (GIDL)) and source/drain junction leakages have become pronounced. Collectively, these leakages are included in what is known as sort channel effects. In well known bulk technologies, for example, short channel effects occur, in part, because dopant implanted in the device source/drain regions out-diffuses radially, such that source/drain regions extended below the device channels. This resulted in a buried leakage path between the source/drain regions and, in some cases in sub-surface channel shorts. Other leakage sources arise, for example, as the distance is reduced between the source and drain junction barrier layers, i.e., from reverse biased junctions. Typically, sub-threshold effects include what is known as subthreshold leakage current, i.e., current flowing drain to source (Ids) at gate biases below threshold for NFETs and above for PFETs. Further, for a particular device, subthreshold current increases with the magnitude of the device's drain to source voltage (Vds) and inversely with the magnitude of the device's VT, drain induced barrier lowering. In addition to the leakage, short channel effects also include what is known as VT roll-off, where the short channel device's current-voltage (I-V) curve exhibits degraded definition.
Lightly doped drains (LDD) are one approach to reducing short channel problems. Essentially, spacers are formed alongside FET gates at source/drain regions. The spacer blocks or attenuates implanting dopant at the gates, spacing the source/drain diffusions away from the gate. A lightly doped region, typically implanted prior to spacer formation, is formed between the heavier source/drain regions and the gate to complete the device. Unfortunately, these lightly doped regions add series resistance at the source and drain of each device, which reduces device currents and degrades circuit performance. Furthermore, as device channel lengths have shrunk well below one micron (1 μm), subthreshold problems have become more pronounced and lightly doped drains does not solve those problems.
Short channel effects improve inversely with body thickness. So, sub-threshold leakage and other short channel effects have been controlled and reduced in silicon on insulator (SOI), by thinning the surface silicon layer, i.e., the device layer. In what is commonly referred fully depleted (FD) SOI on an ultra-thin SOI wafer, the silicon layer is less than 50 nm. Ultra-thin SOI is the leading candidate to continue scaling gate to deep sub 40 nm and beyond. Ultra-thin SOI devices operate at lower effective voltage fields. As a result, the devices can be doped for higher mobility, which in turn increases device current and improves performance. Also, ultra-thin SOI devices have a steeper subthreshold current swing with current falling off sharply as Vgs drops below VT. Unfortunately, however, because source/drain regions are made from the same ultra-thin SOI layer, devices have higher external resistance.
So, to reduce this ultra-thin SOI device external resistance, the semiconductor surface layer is selectively thickened, e.g., using selective epitaxial silicon growth, to produce raised source and drain (RSD) regions. The raised source/drain regions have a larger cross-sectional area and so, lower resistance per unit area (sheet resistance) and so, are effective in overcoming the external resistance problem. Unfortunately, raised source/drains above the silicon layer surface places parallel surface areas at each side of the gate, requiring gaps at gate sidewalls (e.g., spacers) to prevent shorts and, simultaneously causing increased parasitic gate capacitance between the gate and the RSD regions. For example, 30 nanometer (30 nm) RSD regions may increase overlap capacitance for an ultra-thin (˜10 nm) FET with 10 nm sidewall spacers as much as 25 50% (0.08 0.2 femtoFarads (fF) per micron of width) depending upon spacer material. Further, the sidewall spacers add to device area, preventing RSD regions from being placed at the channel ends. Thus, RSD requires a trade-off between reducing external resistance and accepting increased parasitic capacitance.
Both U.S. Pat. No. 6,420,218 B1 to Yu, entitled “Ultra-Thin Body SOI MOS Transistors Having Recessed Source And Drain Regions” and U.S. Pat. No. 6,437,404 B1 to Xiang et al., entitled “Semiconductor-on Insulator Transistor with Recessed Source and Drain” teach recessed source/drain regions as an approach to avoiding or reducing parasitic capacitance. Unfortunately, both Xiang et al. tolerates resistive extensions that connect the device channel to the recessed source/drain regions and that function similarly to LDD, adding series source/drain resistance. Yu teaches forming an ultra-thin channel on defined source/drain recesses and the FET gate between the source/drain recesses, two layer below. Since Yu aligns the gate to the source/drain recess, i.e., because Yu's devices are not self aligned, Yu produces FETs with a relatively wide process variation (i.e., channel length and source/drain overlap), which results in wider spread for circuit performance, i.e., deviation beyond a nominal design point by a significantly larger number of circuits/chips. Thus, previously, one was faced with accepting parasitic device capacitances, series channel resistances and/or looser design tolerances.
Thus, there is a need to reduce external resistance for ultra-thin SOI devices and while minimizing device on resistance.